IBM details next-gen Power 9, will take the fight to Intel's data center strongholds

The story of how Intel rose to dominance in the server and workstation markets was written more than a decade ago. Once upon a time (the late 1980s and early 1990s), various RISC, CISC, and SPARC architectures dominated the high-end PC industry, even as consumer PCs overwhelmingly opted for x86 designs. Intel leveraged both economies of scale and its alliance with Microsoft to push x86 processors into both data centers and workstations. By 2000, Intel had seized the majority of the market, forcing companies like IBM and Sun into smaller and smaller niches.

Today, IBM wants to reverse that trend -- and it thinks Power 9 is the chip to do it. The new cores will come in two flavors; a "scale-out" design meant for large HPC applications and supercomputers with support for four or more CPU sockets and a "scale-up" design with 1-2 sockets. Next Platform(Opens in a new window) reports that there will be four flavors of Power 9 in total, varying in terms of total core count, direct-attached memory, the amount of simultaneous multi-threading (SMT) per-core, and support for various co-processors and other types of compute hardware (ASICS, FPGAs, and GPUs). Power 9 processors can be attached directly to various accelerators rather than communicating via the PCI Express bus. Some of the variants will also support IBM's Centaur memory buffer technology to improve performance and implement an L4 cache.

Challenging Intel, ARM... and AMD?

ARM, AMD, and IBM have all announced fresh challenges to Intel's near-total dominance of the data center market in the past few weeks. Data centers aren't just a lucrative market -- they're one of the only areas of computing that's actually growing. The tablet market is shrinking, smartphone markets in the developing world are maturing rapidly, and the PC industry has been in free-fall for nearly five years. The growth of cloud computing and services like Google and Facebook means that selling to these customers has become essential to top-end server providers.

Each company is making different moves to address these markets. AMD, of course, has Zen, its new architecture that it hopes will offer potent competition for its long-time rival. ARM added a flexible vector instruction set to boost performance in HPC workloads, and IBM is launching an all-new iteration of the Power architecture.

"We started with a 64 bit compute building block and we coupled that with a 64 bit load store building block," Brian Thompto, senior technical staff at IBM said in his Hot Chips presentation. "Each compute building block has a heterogeneous mix of compute, fixed and float, supporting scalar and vector. This allows us to obtain high utilization of our compute resources while also providing seamless exchange of data and shared data paths. It also serves as an efficient building block for managing instruction flow through the machine. We couple two of these 64 bit slices together to make a 128 bit superslice, and this is our physical design building block."

IBM's new cores and their peripheral accelerators will be tied together by its custom on-chip fabric. L3 cache bandwidth is said to be 256GB/s, with support for PCI Express 4.0 (when that standard is available), multiple 25Gb/s "Bluelink" ports (these are used for the attached accelerators and for Nvidia's NVLink 2.0 protocol). Aggregate bandwidth from all these sources is over 7TB/s, though the chip would rarely leverage all of these devices simultaneously.

IBM claims that Power 9 will offer up to 2x the performance of Power 8 per socket -- and it's already courting at least one significant customer. Google has reportedly field-tested Power 8 and has said it would move to Power 9 if doing so would save it 20% power(Opens in a new window) compared with using Intel hardware.