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Intel Talks ARM-Based Products, 10nm, and Beyond

Probably the biggest news at the Intel Developer Forum last week was the company's plans for 10nm production, and particularly that the company would now be offering access to ARM's Artisan physical IP.

August 23, 2016
Intel Technology Pipeline

From a manufacturing point of view, probably the biggest news at the Intel Developer Forum last week was the company's plans for 10nm production, and particularly that the company would now be offering access to ARM's Artisan physical IP. The latter is important because it shows that third-parties who use Intel's 10nm process will have access to the most advanced ARM Cortex cores and related technologies. Intel announced that LG Electronics would be its first 10nm customer; it plans to build a mobile platform based on the Intel process. This indicates that Intel intends to compete more with TSMC, Samsung, and GlobalFoundries in making ARM-based mobile processors.

The announcement came from Zane Ball, general manager of Intel Custom Foundry. I found that quite interesting, but I was equally intrigued by a presentation he and Intel Senior Fellow Mark Bohr gave on the company's advanced technologies.

Logic Transistor Area Scaling TrendLogic Transistor Area Scaling Trend

Bohr discussed the progress Intel has made in 10nm production, saying the company is planning on volume shipments of its first 10nm products in the second half of next year. More interestingly, he said that for its 10nm process the company is getting its historical improvements in transistor gate pitch scaling, and is actually seeing better logic transistor area scaling (which it defines as gate pitch times logic cell height), than it has historically been able to do each generation.

Bohr said that as scaling has slowed at some of its competitors, Intel's 10nm technology could be almost a full generation ahead of the 10nm processes of the other foundries.

(Part of this is a naming question, as the foundries are using the names 14nm, 16nm and 10nm even though that measurement doesn't refer to a specific part of the process anymore. Note that TSMC and Samsung are now both promising that their 10nm processes will be ready next year, whereas historically they have been behind Intel. We won't really be able to see how good the processes are until real products are available, of course.)

Process Technology from 10-KProcess Technology from 10-K

It's been clear that the time between nodes seems to be extending, with the "tick-tock" cadence of a new process now every two years, with microarchitecture changes in between no longer applying. Intel has previously announced that it would be shipping a third generation of 14nm CPUs this year (Kaby Lake, following Skylake and Broadwell).

Derivative TechnologiesDerivative Technologies

Bohr said the company has a "14+" process that provides a 12 percent process performance increase. He also suggested that the 10nm process would actually come in three types, supporting new products over time.

Bohr also talked about how the 10nm process would support a variety of features, including transistors designed for high-performance, low leakage, high voltage, or analog designs, and with a variety of interconnect options. The company hasn't disclosed real performance numbers for the next 14nm chip expected later this year, known as Kaby Lake; and has said even less for the 10nm version expected next year, known as Cannonlake.

It's good to see progress coming, but certainly it's a slowdown from the pace we once expected. At Intel Developer Forum in 2013, the company said it would have 10nm chips going into production in 2015, and 7nm following in 2017.

One thing holding technology back is the lack of successful deployment of EUV lithography systems. EUV is capable of drawing finer lines because it uses light with a smaller wavelength than traditional 193nm immersion lithography. But to date, EUV systems haven't been successfully deployed for volume manufacturing, leading to more double-patterning of traditional lithography, which adds both steps and complexity.

Bohr has noted that EUV will not be ready for 10nm production, and said Intel is developing its 7nm process to be compatible with either all traditional immersion lithography processes (with even more multi-patterning required) or with EUV at some layers. He recently told Semiconductor Engineering that the issues with EUV are uptime and wafers per hour, and said if EUV could resolve those issues, manufacturing could be done at a lower total cost.

At a panel at the conference, Bohr noted that the number of immersion layers is increasing at a dramatic pace, and said he hopes and expects that at 7nm, EUV can replace or slow down the growth of immersion layers.

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About Michael J. Miller

Former Editor in Chief

Michael J. Miller is chief information officer at Ziff Brothers Investments, a private investment firm. From 1991 to 2005, Miller was editor-in-chief of PC Magazine,responsible for the editorial direction, quality, and presentation of the world's largest computer publication. No investment advice is offered in this column. All duties are disclaimed. Miller works separately for a private investment firm which may at any time invest in companies whose products are discussed, and no disclosure of securities transactions will be made.

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