A new leaked set of slides suggests Intel's plans for its Xeon cores could stretch farther into the stratosphere than most of us might have predicted, given the limits of adding more cores to a CPU architecture. This new data purports to show Intel's roadmap for 2015 and beyond, stretching all the way to 28 cores and six memory channels per CPU.
First, a quick refresher. Intel's high-end Xeon platforms lags its desktop introduction cycle by quite some time. Thus, the current line-up of Intel E7 Xeons are still based on the Haswell core, even though that CPU was first introduced on desktops nearly two years ago. According to this roadmap, all of Intel's current platforms hold to more-or-less their current forms until the introduction of Purley, which brings a huge stack of improvements.
The differentiation shown above can be broadly broken down by year, with the introduction of Broadwell-EP in 2015 with up to 22 cores, a Broadwell-EX in 24-core flavor, and finally, Purley, with a Skylake-based CPU and up to 28 CPU cores. Memory channels also take a jump in this version, with clock speeds up to DDR4-2667. It makes sense that Intel would actually bump up the per-CPU memory channels -- it keeps the ratio of cores to memory channels roughly similar to the current E7 Xeons, which feature up to 18 CPU cores and have four channels per chip.
Other major improvements to Purley are covered below:
Skylake Xeons will add AVX-512 support (no word on whether or not this comes to desktops), with on-chip integration of four 10-gigabit Ethernet connections and additional support for add-in accelerator boards through Intel QuickAssist and other optional integrated accelerators. We've covered the company's plans to work with FPGA and ASIC vendors in the past, and it seems we'll see some of that technology finally moving to market by 2017/2018.
The net effect of these gains should be most significant in the high-end PC and HPC space. AVX-512 is based-on previous versions of AVX, but isn't compatible with the 512-bit extensions currently used on Xeon Phi. AVX-512 compatibility in Skylake would imply that Intel widened its registers up to 512-bits for the Xeon flavor of the chip (or fused that capability off in consumer Skylake, if it doesn't come to market). In theory, this would push Intel CPUs up to 32 FPU instructions per clock per core -- 4x what Nehalem offered just 10 years earlier. Actually taking advantage of all that theoretical firepower is more complicated, but between Xeon Phi and Skylake on Purley, Intel clearly wants to slug it out with companies like Nvidia in the HPC space.
