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Apple trademark may hint at processing improvement for next-gen A6 processor

Apple has applied for a trademark on the term "Macroscalar," which refers to …

Apple trademark may hint at processing improvement for next-gen A6 processor

A recent trademark application from Apple for the term "Macroscalar" may give a clue about upcoming improvements for its next-generation mobile processors. The term refers to technology Apple has been working on as far back as 2004, according to Patently Apple, and appears to refer to code optimization techniques that keep processors filled with instructions to run during otherwise repetitive loops.

Apple applied for the trademark for "Macroscalar" in both the US and Hong Kong last week. The trademark application links the term to use with microprocessors as well as mobile devices and software. It turns out that Apple has at least four patents related to what it calls "macroscalar processor architecture," suggesting the trademark is likely connected to an improved processor for its iOS devices.

The "macroscalar" techniques identified in Apple's patents involve optimizing code at compile time to help keep processor pipelines full. Many processors in use today, including the ARM-based designs used by Apple and other mobile device makers, can execute instructions out of order. That is, certain bits of code can run out of sequential order, and the processor takes care of putting all the results back in the right order to make sure the program runs correctly.

These processors also have a pipeline of various depths. The pipeline is, in simple terms, the number of steps an instruction goes through from the start of processing to the finish. As mobile processors become more advanced, they tend to have longer pipelines; the upside is that more instructions can be put in the pipeline to execute, while the downside is that an error can cause a long delay as the pipeline is flushed and reset.

Apple's improvements focus on keeping these longer pipelines full, particularly when running repetitive looping code. The "macroscalar" approach uses compiler optimizations that identify different kinds of looping code. This allows the processor to dynamically optimize the loop code at runtime, by alternatively unrolling the loop, auto-vectorizing the loop to run in parallel, or inserting instructions between code loop iterations to better manage processor utilization. The dynamic optimizations would vary depending on pipeline depth or, in some cases, the presence of additional registers to manage the varied code paths.

The advantage of keeping the pipeline full while the processor isn't idle is two-fold. The processor can execute parallel code threads faster, which should make a computer or device seem more responsive to the end user. It can also get the processor back to a lower-power idle state faster, which can reduce overall power usage. That last quality is particularly important for mobile devices like the iPhone and iPad, which rely on batteries.

The fact that Apple has filed for a trademark for such a specific processor technology is somewhat unusual—the company's trademarks tend to focus less on underlying technology and more on consumer-facing features. This leads us (and others) to believe that Apple expects "Macroscalar" to be an important marketing benefit for upcoming mobile devices, such as a next-gen iPad expected to be revealed within the next month or two.

Apple has reportedly had its next-generation A6 processor in test production since last summer, and may end up being a quad-core design. "Macroscalar" optimizations would be especially useful for such a design.

Channel Ars Technica