Intel's 10nm Cannon Lake Processors To Feature AVX-512 Support
Reading through technical documents is rarely fun, but every so often there are interesting nuggets to uncover. Such is the case with a document (PDF) on Intel's website in regards to its upcoming 10-nanometer Cannon Lake processors. According to the "Intel Architecture Instruction Set Extensions and Future Features Programming Reference," both Cannon Lake and Ice Lake will feature support Advanced Vector Extensions (AVX) 512 instructions (along with a host of other instructions).
AVX-512 first appeared in Intel's Xeon Phi processors.and coprocessors, and later on Intel's Xeon Scalable processors. The instructions were designed to accelerate performance in workstation and server workloads, tasks such as scientific simulations, financial analytics, 3D modeling an analysis, image and audio/video processing, cryptography, data compression, artificial intelligence, and deep learning.
While most of those tasks are out of the realm of what most consumers will do with their systems, there has been increasing focus on AI and deep learning technologies. With Cannon Lake and Ice Lake supporting various AVX-512 instructions, including AVX512F, AVX512CD, AVX512DQ, AVX512BW, and AVX512VL, developers will have an opportunity to do things that are not possible on Kaby Lake and Coffee Lake.
"Intel AVX-512 instructions are important because they open up higher performance capabilities for the most demanding computational tasks. Intel AVX-512 instructions offer the highest degree of compiler support by including an unprecedented level of richness in the design of the instruction capabilities," Intel explains.
"Intel AVX-512 features include 32 vector registers each 512-bit wide and eight dedicated mask registers. Intel AVX-512 is a flexible instruction set that includes support for broadcast, embedded masking to enable predication, embedded floating point rounding control, embedded floating-point fault suppression, scatter instructions, high speed math instructions, and compact representation of large displacement values," Intel continues.
One thing that is not clear is whether those instructions will be limited to higher end SKUs, such as Core i7 chips and/or Extreme Edition variants. Where things get tricky is that, historically, adding AVX-512 support has meant bigger die sizes and higher costs. And that is on the hardware side of things. The other challenge is software support—software has to be updated (or built) to support AVX-512 instructions.
Intel recently showed off a Cannon Lake wafer for the first time. The chip maker expects to ship its first Cannon Lake products by the end of the year, followed by volume production in the first half of 2018.
Thumbnail Image Source: Wikimedia Commons (Rico Shen)
AVX-512 first appeared in Intel's Xeon Phi processors.and coprocessors, and later on Intel's Xeon Scalable processors. The instructions were designed to accelerate performance in workstation and server workloads, tasks such as scientific simulations, financial analytics, 3D modeling an analysis, image and audio/video processing, cryptography, data compression, artificial intelligence, and deep learning.
While most of those tasks are out of the realm of what most consumers will do with their systems, there has been increasing focus on AI and deep learning technologies. With Cannon Lake and Ice Lake supporting various AVX-512 instructions, including AVX512F, AVX512CD, AVX512DQ, AVX512BW, and AVX512VL, developers will have an opportunity to do things that are not possible on Kaby Lake and Coffee Lake.
"Intel AVX-512 instructions are important because they open up higher performance capabilities for the most demanding computational tasks. Intel AVX-512 instructions offer the highest degree of compiler support by including an unprecedented level of richness in the design of the instruction capabilities," Intel explains.
"Intel AVX-512 features include 32 vector registers each 512-bit wide and eight dedicated mask registers. Intel AVX-512 is a flexible instruction set that includes support for broadcast, embedded masking to enable predication, embedded floating point rounding control, embedded floating-point fault suppression, scatter instructions, high speed math instructions, and compact representation of large displacement values," Intel continues.
One thing that is not clear is whether those instructions will be limited to higher end SKUs, such as Core i7 chips and/or Extreme Edition variants. Where things get tricky is that, historically, adding AVX-512 support has meant bigger die sizes and higher costs. And that is on the hardware side of things. The other challenge is software support—software has to be updated (or built) to support AVX-512 instructions.
Intel recently showed off a Cannon Lake wafer for the first time. The chip maker expects to ship its first Cannon Lake products by the end of the year, followed by volume production in the first half of 2018.
Thumbnail Image Source: Wikimedia Commons (Rico Shen)
